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| NJW1341 8input-2output Video Switch with Isolation Amplifier & small AC-coupled Video Driver s GENERAL DESCRIPTION The NJW1341 is 8-Input,2-Output Video Switch. The NJW1341 consists of switch and isolation amplifiers(2input) and Video Driver which features small AC-coupled(1output). All of functions are controlled by I2C Bus. sAPPLICATIONS qCar AVN qAny Video System s FEATURES q Operating Voltage q Small AC-coupled video amplifier (VOUT2) q Isolation Amplifiers(VIN1,2) q 8in-2out Video Switch q Common Mode Rejection Ratio -50dB typ q Bi-CMOS Technology 2 q I C BUS interface q Package Outline s BLOCK DIAGRAM s PACKAGE OUTLINE NJW1341VC3 4.5 to 9.5V SSOP20-C3 VIN1 VGND1 VIN2 VGND2 VIN3 VIN4 + - Buffer VOUT1 + - Mute 6dB 75 Driver 47F 75 + VOUT2 Mute SREF VSAG SSIG SDA I2C BUS SCL VDD V+ GND VIN5 VIN6 VIN7 VIN8 Ver.2 -1- NJW1341 ABSOLUTE MAXIMUM RATING (Ta=25C) PARAMETER Supply Voltage Power Dissipation Operating Temperature Range Storage Temperature Range SYMBOL V + RATINGS VCC:+13,VDD:+7 1,000(note1) -40 to +85 -40 to +150 UNIT V mW C C PD Topr Tstg (note1)At on a board of EIA/JEDEC specification. (114.3 x 76.2 x 1.6mm 2 layers, FR-4) + o ELECTRICAL CHARACTERISTICS(V =5V,Ta=25 C) PARAMETER Operating Voltage 1 Operating Voltage 1 Operating Current 1 Operating Current 2 Operating Current 3 Operating Current 4 Maximum Output Voltage Voltage Gain1 Voltage Gain2 Low Pass Filter Characteristic 1 Differential Gain Differential Phase S/N Ratio Common mode Rejection Ratio CrossTalk SYMBOL VCC VDD ICC1 ICC2 ICC3 Isave Vvom Gv1 Gv2 Gf DG DP SN CMR CT No,signal OUT2 power save OUT1power save OUT1,OUT2 power save f=100kHz,THD=1% OUT1,Vin=1MHz,1.0Vp-p,Sine Signal OUT2,Vin=1MHz,1.0Vp-p,Sine Signal Vin=10MHz /1MHz, 1.0Vp-p sine wave Vin=1.0Vp-p,10step Video Signal Vin=1.0Vp-p,10step Video Signal Vin=1.0Vp-p, 100% White video signal,RL=75, 100KHz to 6MHz Vin=20kHz, 1.0Vp-p Sine Signal Vin=4.43MHz, 1.0Vp-p Sine Signal 2.4 -1.0 5.5 -1.0 TEST CONDITION MIN. 4.5 4.5 TYP. 5 5 25 10 20 2 0 6.0 0 0.5 0.5 60 -55 -60 MAX. 9.5 5.5 40 15 35 4 1.0 6.5 1.0 UNIT V V mA mA mA mA Vp-p dB dB dB % deg dB dB dB -2- NJW1341 s TEST CIRCUIT 1 IN1 VOUT1 20 + 75 1u 2 22u IN1G SREF 19 2k 1u 3 IN2 VSAG 18 68k 68k 1u 0.1u 75 1u 4 IN2G SSIG 17 1u 5 IN3 VOUT2 16 + 75 1u 6 47u IN4 VCC 15 75 75 75 1u 7 0.1u IN5 GND 14 + 47u VCC 4.5V-9.5V 75 1u 8 IN6 VDD 13 + 75 1u 9 47u VDD 4.5V-5.5V IN7 SDA 12 75 1u 10 IN8 SCL 11 75 1u -3- NJW1341 TIMING on the I C BUS (SDA, SCL) SDA 2 tf tr tSU:DAT tf tHD:ST A tSP tr tBUF SCL tHD:ST A S tLOW tSU:STA tHD:DAT tHIGH tSU:ST O Sr 2 P S CHARACTERISTICS OF BUS LINES (SDA, SCL) FOR I C BUS DEVICES I C BUS Load Conditions STANDARD MODE : FAST MODE : 2 Pull up resistance 4k (Connected to +3.3V), Load capacitance 200pF (Connected to GND) Pull up resistance 4k (Connected to +3.3V), Load capacitance 50pF (Connected to GND) PARAMETER Low Level Input Voltage High Level Input Voltage Hysteresis of Schmitt Trigger Inputs Low level Output Voltage (3mA at SDA pin) Output Fall Time From VIHmin to VILmax with a Bus Capacitance from 10pF to 400pF Pulse width of spikes which must be suppressed by the input filter SYM BOL VIL VIH Vhys VOL tof tSP Ii Ci fSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tr tf tSU:STO tBUF Cb VnL VnH Standard mode MIN. 0.0 2.7 0 -10 4.0 4.7 4.0 4.7 0.0 250 4.0 4.7 0.5 1 TYP. MAX . 1.5 5.0 0.4 250 10 10 100 3.45 1000 300 400 - Fast mode MIN. 0.0 2.7 0.25 0 20 +0.1Cb 0 -10 0.6 1.3 0.6 0.6 0.0 100 0.6 1.3 0.5 1 TYP. MAX. 1.5 5.0 0.4 250 50 10 10 400 0.9 300 300 400 - UNIT V V V V ns ns A pF kHz s s s s s ns ns ns s s pF V V Input Current each I/O pin with an Input Voltage between 0.1 and 0.9VDDmax Capacitance for each I/O pin SCL Clock Frequency Data Transfer Start Minimum Waiting Time Low Level Clock Pulse Width High Level Clock Pulse Width Minimum Start Preparation Waiting Time Minimum Data Hold Time Rise Time Fall Time Minimum Stop Preparation Waiting Time Data Change Minimum Waiting Time Capacitive load for each bus line Noise Margin at the Low Level Noise Margin at the High Level NOTE) Minimum Data Preparation Time Cb ; total capacitance of one bus line in pF. NOTE). Please hold the Data Hold Time (tHD:DAT) to 300ns or more to avoid status of unstable at SCL falling edge. -4- NJW1341 s DEFINITION OF I C REGISTER 2 I C BUS FORMAT MSB S Slave Address LSB A 1bit MSB Data 8bit LSB A 1bit P 1bit 2 1bit 8bit S: Starting Term A: Acknowledge Bit P: Ending Term SLAVE ADDRESS MSB 0 0 1 0 0 0 0 R/W=0: Receive Only R/W=1: Data is not transmitted. LSB 0 CONTROL REGISTER DEFAULT VALUE Control register default values are as follows : BIT D7 Data 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 INSTRUCTION CODE BIT D7 Data OUT1 MUTE D6 D5 OUT1 Select D4 D3 OUT2 MUTE D2 D1 OUT2 Select D0 MUTE TABLE MUTE D7 0 1 MUTE D3 0 1 MUTE OFF MUTE ON MUTE OFF MUTE ON OUT1 OUT2 MUTE OFF: Active mode MUTE ON: Power save mode -5- NJW1341 VOUT SELECT TABLE OUT1 Select D6 0 0 0 0 1 1 1 1 D5 0 0 1 1 0 0 1 1 D4 0 1 0 1 0 1 0 1 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8 OUT1 OUT2 Select D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 OUT2 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8 [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. -6- |
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